Among wiring boards for use in connecting a semiconductor component, such as an integrated circuit (IC) or a large-scale integration (LSI), the so-called organic package substrate comprises a wiring laminated portion and a pad array. The wiring laminated portion includes a plurality of dielectric layers comprised of a polymeric material and a plurality of conductor layers. The plurality of dielectric layers and the plurality of conductor layers are alternately laminated so that the dielectric layer may form a first main surface of the wiring laminated portion. The pad array formed at the board side is comprised of a plurality of metal terminal pads formed on the first main surface, which is formed of said dielectric layer, of said wiring laminated portion. A terminal array is formed at a component side on a second main surface of the semiconductor component. The terminal array is formed of a plurality of terminal pads disposed so as to individually correspond to the plurality of metal terminal pads forming the pad array at the board side. The pad array at the board side and the terminal array at the component side are flip-chip bonded via an individual solder joint portion. The first main surface of the wiring board and the second main surface of the semiconductor component are formed of heat-resistant resin for use in protection from melting solder, and are covered by a solder resist layer having a plurality of openings corresponding to each pad location (e.g., see Japanese Patent Application Laid-Open (kokai) No. 2002-031889, which is fully incorporated herein by reference).
In recent years, the trend of high integration and miniaturization of a semiconductor component has been remarkable, and a clearance between terminals provided on a component side array has also been rapidly reduced. In a flip-chip connection structure where the clearance between the terminals is reduced as mentioned above, cracks caused by stress due to a difference in the coefficient of linear expansion between the semiconductor component and the wiring board are likely to occur in a solder joint portion during a cooling process after reflow heat treatment, thereby leading to a connection failure. For example, when the semiconductor component is an Si integrated circuit, the coefficient of liner expansion is around 4×10−6/° C., while the coefficient of linear expansion of a polymeric material that forms a dielectric layer of the wiring board is around 3-4×10−5/° C., nearly ten times larger than that of Si. Therefore, there is a concern that the generation of stress caused by the difference in the coefficient of liner expansion therebetween further leads to the occurrence of cracks. Further, in recent years, considering the environmental pollution problem, conventional Sn—Pb eutectic solder has been replaced by solder not containing Pb, referred to as Pb-free solder. Since the Pb-free solder requires a high reflow temperature, there tends to be a high probability of cracks generated in the above-mentioned solder joint portion after the reflow cooling process.
A problem to be solved by the invention is to provide a wiring board with a semiconductor component which is unlikely to cause defects, such as cracks, in the solder joint portion during the reflow process for flip-chip connection.